A phase-locked loop (PLL) is an electronic circuit that adjusts the frequency of a feedback clock signal based on the frequency of a reference clock signal. Phase-locked loops (PLLs) provide periodic signals for data recovery, data transfer, and other clocking functions in integrated circuits. PLLs often supply a clock signal generated by an oscillator to one or more dividers that divide the clock signal to a lower frequency clock signal for distribution around an integrated circuit or system.
When a PLL is in lock, the phase of the reference clock signal is ideally aligned with the phase of the feedback clock signal. However, a PLL may generate skew between the reference clock signal and the feedback clock signal even when the PLL is in lock. Delay circuits can be added in the paths of the reference and feedback clock signals. The delays of the delay circuits in each integrated circuit are selected based on multiple samples of the integrated circuits.